The present invention relates to data sampling phase shift topology in a voltage controlled oscillator (VCO) based receiver, and more particularly, to a method for performing data sampling control in an electronic device, and an associated apparatus.
According to the related art, in order to overcome the inter symbol interference (ISI) caused by channel loss, a conventional receiver of a conventional system is typically implemented in a manner of changing the sampling threshold to increase the signal-to-noise ratio (SNR). For example, by adopting a decision feedback equalizer (DFE) structure, the conventional receiver may sample data with different thresholds (e.g. thresholds LEV_H or LEV_L) at different time points to compensate 1st post cursor (or TAP1) based on previous data. However, the jitter margins respectively corresponding to different sides of a sampling time point along the time axis may become different in a situation where the TAP1 level increases, which may degrade the overall performance of the whole conventional system. Thus, a novel method and a corresponding architecture are required to improve the jitter margin while maintaining the minimum latency for a data sample path.